Method for fabricating a semiconductor device

ABSTRACT

A method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. A plurality of through substrate vias (TSVs) is formed on the front side. A redistribution layer (RDL) is then formed on the TSVs. The wafer is bonded to a carrier. A wafer back side grinding process is performed to thin the wafer on the back side. An anneal process is performed to re-crystallize the TSVs. A chemical mechanical polishing (CMP) process is performed to polish the back side.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor device, andmore particularly to a TSV interposer and a fabrication method thereof.

2. Description of the Prior Art

A through substrate via (TSV) interposer is a device with electricalthrough vias that is inserted between one or more integrated circuitchips and a mounting substrate. The electrical through vias allow theintegrated circuit chips to be electrically connected to the mountingsubstrate.

As known in the art, the electrical through vias are formed by providingholes in a front side of a silicon substrate, insulating the sidewall ofthe through holes, filling a conductor metal such as copper in thethrough holes by plating or the like, and then grinding the siliconsubstrate on its rear side to expose the other ends of the electricalthrough vias for further connection.

However, the prior art method has some drawbacks, for example, copperextrusion on the exposed ends of the electrical through vias on the rearside of the silicon substrate. Accordingly, there exists a need in theart to overcome the deficiencies described hereinabove.

SUMMARY OF THE INVENTION

In one aspect, the present invention provides a method of fabricating asemiconductor device. A wafer having a front side and a back sideopposite to the front side is prepared. A plurality of through substratevias (TSVs) is formed on the front side. A redistribution layer (RDL) isthen formed on the TSVs. The wafer is bonded to a carrier. A wafer backside grinding process is performed to thin the wafer on the back side.An anneal process is performed to re-crystallize the TSVs. A chemicalmechanical polishing (CMP) process is performed to polish the back side.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the embodiments, and are incorporated in and constituteapart of this specification. The drawings illustrate some of theembodiments and, together with the description, serve to explain theirprinciples. In the drawings:

FIG. 1 to FIG. 6 are schematic, cross-sectional diagrams showing anexemplary method for fabricating a semiconductor device according to oneembodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings, which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments maybe utilized and structural changes maybe made without departing from the scope of the present invention.

The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled. One or more implementations of thepresent invention will now be described with reference to the attacheddrawings, wherein like reference numerals are used to refer to likeelements throughout, and wherein the illustrated structures are notnecessarily drawn to scale.

The terms wafer and substrate used herein include any structure havingan exposed surface onto which a layer is deposited according to thepresent invention, for example, to form the circuit structure such as aredistribution layer (RDL). The term substrate is understood to includesemiconductor wafers, but not limited thereto. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon.

Please refer to FIG. 1 to FIG. 6. FIG. 1 to FIG. 6 are schematic,cross-sectional diagrams showing an exemplary method for fabricating asemiconductor device according to one embodiment of the invention.

As shown in FIG. 1, first, a wafer 100 is provided. The wafer 100 maycomprise a silicon interposer wafer, but not limited thereto. The wafer100 may have an initial thickness that may range between 600 and 800micrometers, for example, 770 micrometers. The wafer 100 has a frontside 100 a and a back side 100 b.

A plurality of through substrate vias (TSVs) 101 may be formed in thewafer 100 on the front side 100 a of the wafer 100. The method formaking of the TSVs 101 is well known in the art. For example, to formthe TSVs 101, TSV holes are formed on the front side 100 a of the wafer100 to a predetermined depth below a major surface of the wafer 100. Theinterior surface of each TSV hole maybe insulated by a dielectric layersuch as silicon oxide layer 103. Metals including but not limited todiffusion barrier metals and copper 102 are deposited into the TSVholes. The front side 100 a of the wafer 100 may be subjected to apolishing process and an anneal process.

As shown in FIG. 2, according to the illustrated embodiment, aredistribution layer (RDL) 110 may be formed on the front side 100 a ofthe wafer 100. The RDL 110 may comprise at least one dielectric layer112 and at least one metal layer 114. The TSVs 101 may be connected withthe metal layer 114. A plurality of bumps 116 such as micro-bumps may beformed on the RDL 110 for further connections. The bumps 116 maybedirectly formed on respective contact pads formed in the metal layer114.

It is to be understood that the RDL structure in figures is forillustration purposes only. In some embodiments, the RDL 110 maycomprise multiple dielectric layers and multiple metal interconnectionfeatures or traces in the multiple dielectric layers. In still anotherembodiment, semiconductor dies may be mounted on the front side 100 aand sealed by a molding compound (not shown).

As shown in FIG. 3, subsequently, wafer 100 is adhered to a carrier 200.For example, the carrier 200 may be a glass carrier, a silicon carrier,or the like, but not limited thereto. The bumps 116 face toward, and maycontact, the carrier 200. Optionally, an adhesive layer (not explicitlyshown) may be used when bonding the carrier 200 with the wafer 100.

As shown in FIG. 4, subsequently, after forming the carrier 200, theback side 100 b of the wafer 100 is subjected to a wafer back sidegrinding process to thin the wafer 100. A portion of the wafer 100 isremoved from the back side 100 b of the wafer 100. Optionally, achemical mechanical polishing (CMP) process may be performed to revealthe TSVs 101 from the back side 100 b of the wafer 100.

As shown in FIG. 5, the back side 100 b of the wafer 100 is thensubjected to an anneal process to re-crystallize the copper 102 of theTSVs 101 near the back side 100 b of the wafer 100. According to theillustrated embodiment, the anneal process is preferably carried out ata temperature of about 200° C. According to the illustrated embodiment,copper extrusion 130 may occur on the exposed ends of the TSVs 101.

As shown in FIG. 6, the back side 100 b of the wafer 100 is thensubjected to another CMP process to polish away the copper extrusion 130from the back side 100 b of the wafer 100. Subsequently, a passivationlayer (not shown) may be formed on the back side 100 b of the wafer 100.Optionally, redistribution layer may be formed on the back side 100 b ofthe wafer 100. Subsequently, the carrier 200 may be de-bonded.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method of fabricating a semiconductor device, comprising: formingvias extending into a wafer from a front side thereof; filling the viaswith copper; forming a redistribution layer (RDL) consisting of at leastone dielectric layer and at least one metal layer comprising traces overthe front side of the wafer, the traces connected to the copper fillingthe vias; forming bumps on and connected to contact pads of the traces;bonding front side of the wafer to a carrier; performing a grindingprocess to a back side of the wafer to thin the wafer on the back sideto expose an end surface of the copper filling each of the vias isexposed to form through substrate vias (TSVs); after the end surface ofthe copper filling of each of the TSVs is exposed, performing an annealprocess to re-crystallize copper filling the TSVs and form a copperextrusion on the end surface of copper filling of each of the TSVs; andperforming a chemical mechanical polishing (CMP) process to polish theback side of the wafer and remove the copper extrusions.
 2. The methodof fabricating a semiconductor device according to claim 1, whereinforming the vias extending into the wafer from the front side thereofcomprises: forming holes from the front side of the wafer to apredetermined depth below the front side of the wafer; and insulatinginterior surfaces of the holes with a dielectric layer before fillingthe holes with copper.
 3. The method of claim 1, further comprisingperforming another CMP process on the back side of the wafer afterperforming the grinding process and before performing the annealprocess.
 4. The method of claim 1, wherein the anneal process is carriedout at a temperature of about 200° C.
 5. (canceled)
 6. (canceled)
 7. Themethod of claim 1 further comprising de-bonding the carrier from thewafer after performing the CMP process.
 8. The method of claim 1,wherein forming vias extending into a wafer from a front side thereofcomprises forming vias into a semiconductor wafer.
 9. The method ofclaim 8, further comprising selecting the semiconductor wafer tocomprise silicon.
 10. The method of claim 1, wherein forming viasextending into a wafer from a front side thereof comprises forming viasinto an in-process semiconductor structure.
 11. The method of claim 1,wherein forming a redistribution layer (RDL) consisting of at least onedielectric layer and at least one metal layer comprising traces over thefront side of the wafer further comprises forming an RDL comprisingmultiple dielectric layers and at least one of multiple interconnectionfeatures and traces in the multiple dielectric layers.
 12. The method ofclaim 1, further comprising selecting the carrier to be a glass carrieror a silicon carrier.
 13. The method of claim 1, wherein forming viasextending into a wafer from a front side thereof comprises forming viasextending into a wafer of an initial thickness of between 700 μm and 800μm.
 14. The method of claim 1, further comprising, after performing achemical mechanical polishing (CMP) process to polish the back side ofthe wafer and remove the copper extrusions, forming a passivation layerof the back side of the wafer.
 15. The method of claim 1, furthercomprising, after performing a chemical mechanical polishing (CMP)process to polish the back side of the wafer and remove the copperextrusions, forming another redistribution layer (RDL) on the back sideof the wafer.